May 14, 2025
P1.1.11-Wed (sub. #131)
Island 1.1 on level -1.
Karim Ait Lahssaine, CEA-Leti, Olivier Savry, CEA-Leti
CIAMH : Confidentiality, Integrity and Authentication across the Memory Hierarchy
May 14, 2025
P1.1.11-Wed (sub. #214)
Island 1.3 on level -1
Damien Couroussé, Univ. Grenoble Alpes, CEA-List. Mathieu Jan, CEA-List.
Pre-silicon Security Analysis of\ RISC-V Processors to Fault Injection Attacks
May 14, 2025
P1.1.11-Wed (sub. #56)
Island 3.1 on level -3
Ivan Sarno, CEA-List. Stefano Di Matteo, CEA-Leti. Emanuele Valea, CEA-List. Cyrille Chavet, Université de Grenoble - TIMA.
RISC-V-based Acceleration Strategies for Post-Quantum Cryptography
May 14, 2025
P1.1.11-Wed (sub. #52)
Island 3.1 on level -3
Alessandra Dolmeta, Politecnico di Torino. Stefano Di Matteo, CEA-Leti. Emanuele Valea, CEA LIST. Mikael Carmona, CEA-Leti. Antoine Loiseau, CEA-Leti. Maurizio Martina, Politecnico di Torino. Guido Masera, Politecnico di Torino
TYRCA: A RISC-V Tightly-coupled accelerator for Code-based Cryptography
May 14, 2025
P2.1.03-Wed (sub. #136)
Island 2.1 on level -2
Billal Ighilahriz, CEA-Leti. Olivier Savry, CEA-Leti
Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV DV, RVLS, and Questa/UVM
May 14, 2025
P1.1.11-Wed (sub. #185)
Island 2.3 on level -2
Ayoub Mouhagir, CEA-List. Fatma Jebali,
CEA-List. Oumaima Matoussi,
CEA-List. Caaliph Andriamisaina,
CEA-List. Anthony Philippe,
CEA-List.
Towards Efficient Modeling and Validation of Scalable Chiplet-based Platforms
May 13, 2025
P2.1.07-Tue (sub. #34)
Island 2.1 on level -2
Eric Guthmuller, Univ. Grenoble Alpes, CEA-List. Tanuj Khandelwal, Univ. Grenoble Alpes, CEA-List
Implementing out-of-order issue in CVA6 for efficient support of long variable latency instructions
May 14, 2025
P1.1.11-Wed (sub. #35)
Island 2.2 on level -2
Eric Guthmuller, Univ. Grenoble Alpes, CEA-List. Jérôme Fereyre, Univ. Grenoble Alpes, CEA-List.
RISC-V based GPGPU on FPGA: A Competitive Approach for Scientific Computing ?