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VLSI 2020 Paper Details First Proof of Integration of FDSOI CMOS Devices Processed at 500°C, for Further 3D Monolithic Integration
Integration of CMOS devices is now possible at 500°C on top," said CEA-Leti scientist Claire Fenouillet-Beranger. "This proof of concept gives more and more credibility to this sequential integration for applications requiring high densit
3D sequential integration becomes more and more attractive for More Moore and More than Moore applications," the paper reports. "One of the main advantages of this 3D technology vs. a die-to-die one, for instance, is the major gain of density brought by the nanometer-scale lithographic alignment between the two levels. However, one of the most important challenges is to implement at low temperature high performance CMOS devices for the upper level, after fabrication of the bottom level devices.
"The maximum temperature regarding bottom device's silicide integrity and inter-tier interconnections preserved reliability should not exceed 500°C for a couple of hours," the paper reported. "Several low-temperature devices have been published in literature, but up to our knowledge, this is the first proof of integration of CMOS devices processed at a temperature of 500°C, fully compatible with advanced FDSOI platform technologies."
CEA is a French government-funded technological research organisation in four main areas: low-carbon energies, defense and security, information technologies and health technologies. A prominent player in the European Research Area, it is involved in setting up collaborative projects with many partners around the world.