The challenge: achieving precise alignment in lithography
"Electronic chips are becoming increasingly complex and compact. To maximize space, a new architecture separates power and signal networks across different transistor layers," explains Ivanie Mendes, project manager and lithography researcher-engineer at CEA-Leti.
This architecture is known as Backside Power Delivery Network and it relies on transferring one or more transistor layers from one silicon substrate to another by bonding wafers together.
“The challenge in lithography is to achieve precise alignment of the next exposure steps—down to just two nanometers," adds Ivanie Mendes.
Understanding the causes of distortion
The bonding process used in this application is direct bonding, meaning it occurs spontaneously without adhesives.
"Even though the process is spontaneous, we initiate it," says Frank Fournel, bonding expert at CEA-Leti. "A bonding wave propagates between the wafers, pushing out air as it moves. But that's where the problem arises—the air creates resistance, generating an overpressure of roughly three bars. It deforms the wafers as the bonding wave propagates, disrupting the alignment and making it difficult to maintain the required two-nanometers precision."
A comprehensive strategy to overcome distortion issues
CEA-Leti launched a dedicated program to study the link between bonding-induced distortion and lithography alignment.
"Our team designed and manufactured specific test vehicles to analyze these distortions," explains Marie-Line Pourteau, lithography researcher-engineer at CEA-Leti. "We also developed a groundbreaking metrology technique in collaboration with the leading manufacturer ASML."
CEA-Leti's researcher-engineers were able to precisely map bonding-induced distortions by collecting over 18,000 measurement points per bonded pair. A collaborative effort with the equipment manufacturer EVG then enabled the research team to minimize the deformations caused by the bonding process.
Significant breakthroughs with global recognition
The team identified key parameters affecting distortion, with surface preparation playing a crucial role.
"By optimizing these parameters, we achieved an 85% reduction in distortion," highlights Karine Abadie, project manager and bonding researcher-engineer at CEA-Leti.
This breakthrough provides practical solutions for the next generation of microelectronics chips manufacturing. The researcher's work was recognized at major international conferences, such as SPIE Advanced Lithography and Patterning and IITC, where the entire project team was honored with the award for best paper.
With these advances, CEA-Leti continues to push the boundaries of semiconductor innovation, ensuring that tomorrow's chips are smaller and more powerful thanks to unparalleled manufacturing precision.