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Artificial Intelligence of Things (AIoT) proof-of-concept chip presented at VLSI 2020


Researchers at CEA-Leti and CEA-List developed the world's first low-power IoT node with an integrated artificial intelligence accelerator combined with an ultra-fast wake-up time. They presented the research that led to the groundbreaking chip* at the 2020 Symposia on VLSI Technology and Circuits (VLSI) on June 14.

Published on 19 June 2020
​Researchers at CEA-Leti and CEA-List developed the world's first low-power IoT node with an integrated artificial intelligence accelerator combined with an ultra-fast wake-up time. They presented the research that led to the groundbreaking chip* at the 2020 Symposia on VLSI Technology and Circuits (VLSI) on June 14.


When it comes to artificial intelligence, most computing is done in the cloud, far from the source of the data. Tighter integration—moving computing resources closer to where the data is collected—reduces power consumption, latency, and potential privacy breaches. Highly energy-efficient AI accelerators combined with low-power, versatile IoT nodes would be needed for this kind of integration to be viable. The CEA's proof-of-concept SamurAI chip couples a low-power IoT node with an energy-efficient machine learning (ML) accelerator. A dual-subsystem scheme allows this AIoT node to address a wide range of computing applications while delivering optimal energy efficiency. 


        

  
SamurAI system architecture, with Always-Responsive and On-Demand sub-systems    


       Die micrograph of SamurAI with building blocks, 4.5mm




  • In low-power mode, an event-driven asynchronous controller core with instant-on capabilities (207ns) executes short, sporadic computing tasks at 1.7MOPS. 

  • In high-performance mode, a RISC-V low-power core coupled with an energy-efficient ML accelerator with 64 processing engines executes the most demanding tasks. The node delivers up to 36GOPS and 1.3 TOPS/W when running ML tasks. Together, the dual-subsystem scheme with asynchronous logic and ML accelerator enable a 15,000-fold peak-to-idle power reduction, evidence of the architecture's versatility.

 

The SamurAI chip, made using STMicroelectronics FDSOI28 technology, is equipped with a wake-up radio to receive small messages, a cryptographic accelerator to secure communications, external non-volatile memory for deep sleep mode, and power management with adaptive voltage scaling for further circuit-level energy reduction. It delivers 4 times better computing performance, 3.5 times better power efficiency, and 2 times better power reduction than similar IoT nodes.

It was tested on a people-counting and scene-classification scenario, where it slashed the total power consumption of the system (which included a video camera, sensor, and radio module) by a factor of 3 with the dual-subsystem scheme and by a factor of 2.3 when the ML accelerator is used instead of the RISC-V core. The privacy of the data captured was protected.  


*"SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000x Peak-to-Idle Power Reduction, 207ns Wake-up Time and 1.3TOPS/W ML Efficiency".

 


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