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VLSI 2021 Symposium Paper also Demonstrates First Low-Temperature Devices on Low-Temperature Silicon-on-Insulator Substrate Fabricated with Smart CutTM Technology
GRENOBLE, France – June 17th, 2021 – CEA-Leti, a research institute at CEA, has demonstrated record performance in top-tier nMOSFETs using the institute’s 3D low-temperature (LT) sequential integration technology, CoolCubeTM.
The paper being presented virtually at the VLSI 2021 Technology Symposium also provides guidelines for the junction optimization to improve the performance of devices fabricated with a maximum temperature of 500°C. In addition, for the first time, LT nMOS devices were integrated on LT silicon-on-insulator (LTSOI) fabricated with Smart CutTM technology.
Shay Reboh, an author of the paper, said MOSFETs for logic or analog applications, as well as the co-integration with miniaturized smart sensors, will be the primary uses for 3D sequential integration. “The technological and commercial benefits of low-temperature layer transfer using Smart CutTM also include cost reduction and recycling of the donor wafer, compared to the use of SOI wafers, plus etch back,” he said.
CEA is a French government-funded technological research organisation in four main areas: low-carbon energies, defense and security, information technologies and health technologies. A prominent player in the European Research Area, it is involved in setting up collaborative projects with many partners around the world.