You are here : Home > Leti Sessions @ IEDM Conf 2017

Event


Leti Sessions @ IEDM Conf 2017

From 12/4/2017 to 12/6/2017
Hilton San Francisco Union Square, San Francisco California

SAVE THE DATE!

Leti will present 11 papers at IEDM Conference 2017 in San Francisco, Dec. 2-6, including three invited papers on 3D sequential integration, advanced memory solutions and stacked nanowires FETs. It also will host a workshop covering "Pioneering Technologies for More than Moore" on Dec. 3, anchored by a keynote talk from GlobalFoundries executive John Pellerin. Check out our workshop program here.

This year, Leti's scientific papers include:

  • Monday, Dec. 4

        1:35 pm - Session 3.1:
        "3D Sequential Integration: Application-driven technological achievements and guidelines" (Invited)
        Location: Grand Ballroom B

        2:25 pm - Session 2.3: 
        "In-depth investigation of programming and reading operations in RRAM cells integrated with Ovonic Threshold
         Switching (OTS) selectors"
        Location: Grand Ballroom B

        4:05 pm - Session 7.6:
        "Thermal effects in 3D sequential technology"
        Location: Continental Ballroom 6

  • Tuesday, Dec. 5

       10:45 am - Session 16.5:
        "Industrialised SPAD in 40 nm Technology"
        Location: Continental Ballroom 7-9

       11:35 AM - Session 14.6:
       "Improvement of HfO2 based RRAM array performances by local Si implantation"
        Location: Continental Ballroom 5

       2:05 pm - Session 24.1:
      "Hybrid III-V/Si DFB laser integration on a 200 mm fully CMOS-compatible silicon photonics platform"
      Location:  Continental Ballroom 6

      2:55 pm - Session 20.3:
     "Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for
      ultra-low-voltage operation"
      Location:  Grand Ballroom B

     3:40 pm - Session 19.4:
     "Advanced memory solutions for emerging circuits and systems" (Invited)
     Location:  Grand Ballroom A

  • Wednesday, Dec. 6

       9:30 am - Session 29.2:
      "Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs" (Invited)
       Location:  Grand Ballroom B

      9:30 am - Session 32.2
      "High performance low temperature FinFET with DPSER, gate last and Self Aligned Contact for 3D sequential 
       integration"
       Location:  Continental Ballroom 4

      9:55 am - Session 34.3:
      "Developments in 300mm silicon photonics using traditional CMOS fabrication methods and materials (Invited)"
      Location:  Imperial Ballroom B

 

Practical information

Hilton San Francisco Union Square
333 O’Farrell Street
San Francisco, CA 94102
Phone:(415) 771-14000

Top page

Events

RSS feed