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Congratulations to Karine Abadie and Ivanie Mendes on their 'Best Paper Award' at IITC!


​​​​​​​​​​​​​​​​The project team led by Karine Abadie, a bonding process engineer, and Ivanie Mendes, a lithography process engineer, was recognized with a 'Best Paper Award' at IITC. This international conference is dedicated to interconnects and BEOL¹/MEOL² metallization in microelectronics. In collaboration with industrial partners ASML and EVG, the research team developed an innovative metrology method to better understand the stress induced by the bonding step in silicon wafer and its impact in lithography.
Published on 27 March 2025

For several years, CEA-Leti has been a key player in research by actively contributing to the development of technological sovereignty at both national and European levels. The work carried out by Karine and Ivanie’s team aligns with this ongoing objective to meet the current needs of the microelectronics industry: designing microprocessors that are both smaller and more efficient. The advances made through this project help strengthen Europe’s expertise in microelectronics manufacturing processes.
 
Karine Abadie graduated from the School of Mechanics and Microelectronics (ENSMM) in Besançon. She joined the research institute in 2011, beginning her career as a 3D integration process engineer before moving in 2013 to work for equipment manufacturer EVG as a bonding process engineer associated with CEA-Leti. In 2020, she joined CEA-Leti’s team in the same field. Ivanie Mendes specialized in nanosciences physics at Grenoble-INP Phelma engineering school. She first joined CEA-Leti in 2017 for an end-of-studies internship before joining the lithography team in 2019.

Direct Bonding-Induced Distortion Characterized by Immersion Scanner: A Breakthrough Technique​

A newly developed approach in 3D integration, the "backside power delivery network" technology, aims to construct the power distribution network for transistors on the backside of the chip rather than on its active surface. This innovative architecture frees up space, thus increasing transistor density. The process involves transferring the transistor layer from one silicon substrate to another through a bonding step. However, the challenge is to precisely (< 2nm) build the upper levels upon this transferred transistor layer.
 
The groundbreaking contribution of CEA-Leti engineers, as outlined in their IITC publication, lies in their ability to characterize, both locally and globally, the deformations induced by direct bonding sequence on the thin transferred silicon film. Direct bonding is initiated when two substrates come into contact at a single point, triggering a bonding wave that expels air trapped between them. However, this process generates an overpressure of nearly 3 bars!
 
This overpressure distorts the substrates relative to each other, causing misalignment at the bonding interface. The key challenge in lithography is ensuring that subsequent layers are accurately aligned despite these distortions, with precision down to a few nanometers.
 
To tackle this challenge, Karine and Ivanie’s team developed an innovative metrology technique, implemented on the immersion scanner in partnership with ASML. This methodology enables the precise mapping of distortions that occur during bonding. Concurrently, R&D was implemented with EVG to mitigate the stress induced during bonding.
 
Through this research project, significant improvements have been made in understanding and managing bonding-induced deformations. This positions CEA-Leti as a leader in addressing industrial challenges in advanced microelectronics, particularly for sub-10nm technology nodes.​


This project showcased CEA-Leti’s scientific and technical expertise in microelectronics processing to better serve our industrial partners." - Karine Abadie
"Thanks to this collaboration, we often say among ourselves that lithography helped us understand bonding." - Ivanie Mendes

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