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From 4/1/2019 to 4/4/2019
Maison Minatec, 3 Parvis Louis Néel, 38000 Grenoble, France.

​The annual SOI-focused conference also addressing advanced silicon-based technologies will be held in Grenoble, France, on April 1-4, 2019.

This Conference will gather together all scientists and engineers working in the field of new materials and advanced nanoscale devices. One of the key objectives of the conference will be to promote collaboration and partnership between different academia, research and industry players.

CEA-Leti is an official partner of the event.

Conference papers:

  1. Impact Of Inter-Tier Coupling On Static And Noise Performance in 3D Sequential Integration Technology, P. Sideris,

  2. C.Theodorou, L. Brunet, P. Batude, G. Sicard, Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, CEA-LETI France

  3. Vertical Heterojunction Ge0.92Sn0.08/Ge Gate-All-Around Nanowire pMOSFETs, Mingshan Liu, K. Mertens, N. von den Driesch, T. Grap, Stefan Trellenkamp, J.M. Hartmann, J. Knoch, D. Buca, Qing-Tai Zhao, 1Peter-Grünberg-Institute (PGI 9) and JARA-Fundamentals of Future Information Technologies, Forschungszentrum Jülich, 52428, Germany, RWTH Aachen University, Germany, HNF Jülich, Germany, CEA-LETI, France

  4. Thin film BIMOS transistor for low power spiking neuron cell in 28nm FD-SOI CMOS technology, P. Galy, T. Bedecarrats, C. Fenouillet-Beranger, S. Cristoloveanu, CEA-LETI, IMEP, MINATEC, France

  5. Pure boron monolayer to boost A2RAM performance, F. Tcheme Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, T. Poiroux, CEA-LETI, IMEP-LAHC, France

  6. Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors, Dae-Young Jeon, So Jeong Park, M. Mouis, S. Barraud, Gyu-Tae Kim, G. Ghibaudo, Korea Institute of Science and Technology, Korea, IMEP-LAHC, CEA-LETI, France

  7. Effect of reduced oxygen partial pressure SiGe condensation for the fabrication of ultra-thin SGOI substrates, D. Valenducq, O. Gourhant, E. Blanquet, F. Deprat, F. Abbate, V. Guyader, S. Pélissier, D. Rouchon, STMicroelectronics, SIMaP, CEA-LETI, FranceBack-bias impact on variability and BTI for 3D-monolithic 14nm FDSOI SRAMs applications, D. Bosch, F. Andrieu, X. Garros, L. Ciampolini, A. Makosiej, O. Weber, J. Lacord, J. Cluzel, B. Giraud, G. Cibrario, L. Brunet, P. Batude, C. Fenouillet-Béranger, D. Lattard, J. P. Colinge, F. Balestra, M. Vinet, CEA-LETI, STMicroelectronics, UGA, INP, France

  8. RF characterization and small signal extraction on 22 nm CMOS fully-depleted SOI technology, O.Kane, L.Lucci, P.Scheiblin, S. Lepilliet, F.Danneville,, CEA-LETI, IEMN, France

  9. gm/ID-derivative Method for Threshold Voltage Extraction in Junctionless MOSFETs, T. Rudenko, A. Nazarov, V. Kilchytska, S. Barraud , D. Flandre, V. E. Lashkaryov Institute of Semiconductor Physics, Ukraine, Univ. cath. Louvain, Belgium, CEA-LETI, France

  10. Design and development of silicon-based 3D arrays of coupled Quantum Dots, Y.J. Kim, B. Bertrand, L. Hutin, S. De Franceschi, T. Meunier, M. Vinet, CEA-LETI, CEA-INAC, Institut Néel, UGA, France

  11. Modeling of the bridge threshold voltage in A2RAM cell, F. Tcheme Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, T. Poiroux, CEA-LETI, IMEP-LAHC, France

Practical information

​Program & Registration :

When ?

  • April 1-4, 2019.

Where ?
  • Maison Minatec, 3 Parvis Louis Néel, 38000 Grenoble, France.

Contact :

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