What's INTACT?

IntAct consists of a 96 core architecture composed of 6 chiplets (FDSOI 28nm) 3D-stacked onto an active silicon interposer (CMOS 65nm), fully processed, packaged and tested. 

• The chiplet-based architecture benefits of advanced 3D integration scheme including TSV-middle and ultra-fine pitch die-to-die interconnects,
• The active interposer integrates Network-on-Chip's, DC-DC converters, and System IO's.
• The prototype has been assessed morphologically and electrically. Finally, the structural test of the IntAct prototype was reached and is showing results well within expectations onto the application board.
• These results pave the way to the design of future high efficiency systems for high performance computing. 
  

 Applications

In the context of HPC (High Performance Computing) and AI (Artificial Intelligence) acceleration, there is an ever increasing demand of computing capacity and solutions for specialization and energy efficiency..

• Partitioning a large single die in a multitude of smaller dice leads to reduced costs in advanced technology nodes, and also to high level of application specialization.
• Chiplets can be highly configurable and optimized using adequate technologies: generic computing cores chiplet, GPU chiplet, FPGA fabric chiplet, AI accelerators chiplet for energy efficient AI kernels, advanced memoires such as HBM.
• Finally, IP and chiplet re-use is also one key advantage of such active interposer integration.

 What's new?

The main IntAct prototype innovations are related to both technology and architecture:Technologies 3D avancée : 

• Advanced 3D Technology: about 150,000 connections between the chiplets and the interposer using ultra fine pitch die to die interconnects (copper pillar 20μm pitch), 14,000 TSVs (10 μm diameter, pitch 40μm) through the active interposer, with 6 chiplets (FDSOI 28nm, 20mm²) 3D-stacked onto the active interposer (CMOS 65nm, 220mm²).
  

• Advanced 3D Architecture : Active Interposer offers Network-on-Chip for chiplet-to-chiplet communication, scalable and configurable cachecoherent L1/L2/L3 architecture, integrated DC-DC converters for chiplet power supplies, system level IO's, Design-for-Test infrastructure, the whole architecture providing a cache coherent 96-core system.